`include "defines.v"
`timescale 1ns / 1ns
module ctrl(
    input wire rst,

    //from ex
    input wire jump_flag_i,
    input wire[`InstAddrBus] jump_addr_i,

    //from clint
    input wire hold_flag_clint_i, 


    output reg jump_flag_o,
    output reg[`InstAddrBus] jump_addr_o,
    output reg[`Hold_Flag_Bus] Hold_flag_o


);
    always @ (*)
        begin
            if (rst == `RstEnable)
                begin
                    Hold_flag_o = `Hold_None;
                    jump_addr_o = `ZeroWord;
                    jump_flag_o = `JumpDisable;
                end
            else
                begin
                    jump_addr_o = jump_addr_i;
                    jump_flag_o = jump_flag_i;
                    if (jump_flag_i == `JumpEnable || hold_flag_clint_i == `HoldEnable )
                        begin
                            Hold_flag_o = `Hold_Id;
                        end
                    else
                        begin
                            Hold_flag_o = `Hold_None;
                        end
                        
                end
        end



endmodule